As the trend toward advanced microprocessors, e.g. central processing units (CPUs), with more transistors and higher frequencies continues to grow, computer designers and manufacturers are often faced with corresponding increases in power and energy consumption. Particularly in mobile devices, such as laptop computers, wireless handsets, personal digital assistants, tablet computers, etc., increased power consumption can lead to overheating, which can negatively affect performance and significantly reduce battery life. Because batteries typically have a limited capacity, running the processor of a mobile device more than necessary could drain the capacity more quickly than desired.
To manage power consumption, today's high end CPUs have two distinct power-down modes—C-states and S-states. In C-states the CPU is put into sleep mode while maintaining context and appearing architecturally active to the system, also referred to as an idle state. In S-states the CPU is powered off and a boot process is required to restart it. Operating systems typically support a built-in power management software interface such as Advanced Configuration and Power Interface, (ACPI), an open industry specification standard first published in 1996, in which the CPU is placed into lower power sleep states based on reduced activity or demand. Among other aspects, the ACPI defines the lower power sleep states as a progression of C-states that can be supported by processors and/or chipsets.
For example, in ACPI, C0 is defined as the Run Time state in which the processor operates at high voltage and high frequency, C1 is defined as the Auto HALT state in which the core clock is stopped internally, C2 is defined as the Stop Clock state in which the core clock is stopped externally, and C3 is defined as a Deep Sleep state in which the Phase Locked Loops (PLLs) are shut down to turn off all processor clocks. In the C4 state, the voltage applied to a processor that is already in the C3 state is lowered to reduce leakage without jeopardizing state retention in the cores and caches.
Alternatively or in addition to ACPI, high end CPUs employ proprietary power management interfaces that define other C-states, referred to as enhanced C-states, in which different combinations of processor clocks are turned off and the processor voltage is reduced to a lower data retention point to achieve even deeper sleep states and greater reductions in power consumption. These additional sleep states are generally characterized by similar or equivalent semantics as the ACPI C-states, in which a higher numbered C-state generally consumes lower power than a lower numbered C-state, albeit with generally higher exit latencies.
A C-state can refer to the state of a single core. However, most modern processors are actually composed of several CPUs, such as the Intel Core Duo, which has 2 cores, or the Intel Core-2 Quad, which has 4 cores. Although each core has its own idle state, the multiple cores in a processor often share resources, such as the L2 cache or the clock generators. Therefore a processor generally can enter a particular C-state only if all of the cores in that processor are able to enter that C-state, sometimes referred to as a package C-state.
In operation, to enter the deeper sleep states, a power management interface typically detects a time slot in which there are no new or pending interrupts to the processor. The power management interface then uses an input/output (I/O) controller or other chipset feature to place the processor into the deeper sleep states. For example, entry into deeper sleep states is typically achieved by referencing an external voltage reference in a processor voltage regulator (VR) circuit and regulating to this reference voltage whenever a platform “Deeper Sleep” signal such as a DPRSLPVR signal or other similar signal is asserted by an I/O controller or other integrated circuit. The VR then transitions from a first voltage to a second lower voltage associated with the deeper sleep state including, for certain sleep states, a zero voltage. Upon exiting the deeper sleep state, the VR transitions back to a higher voltage within a specified time window.
After a processor has been placed into the deeper sleep state, a break event or interrupt from the operating system or another source may be sent to the chipset, and the chipset will then allow the processor to exit the deeper sleep state. The ability to transition between various power management states, including deeper sleep states, enables power consumption and dissipation to be reduced and battery life to be increased.